This invention relates generally to data processing control apparatus, and more particularly to improved accessing control means and methods for providing access, in accordance with a predetermined priority basis, for a plurality of requestors to a commonly shared unit, channel or service. For example, the requestors may comprise a plurality of data processing ports, the commonly shared unit may be a memory storage unit, and the priority may be on a random selection basis, that is, requests are granted on a first-come, first-serve basis.
A typical prior art three-port priority system is illustrated in FIG. 1 a plurality of ports P-1, P-2 and P-3 provide r request signals R-1, R-2 and R-3 to priority logic circuitry 10 which determines which one of the ports P-1, P-2 or P-3 is to be granted access to the commonly used unit by activating a corresponding one of the grant outputs G-1, G-2 or G-3.
If only one of the request signals R-1 to R-3 in the prior art system of FIG. 1 is active, the priority logic circuitry 10 simply grants access to the respective one of the ports P-1 to P-3 corresponding thereto. However, if more than one of the request signals R-1 to R-3 is active at the same time, the priority logic circuitry 10 must determine which of the corresponding ports P-1 to P-3 is to be granted access.
There are various possible ways known in the art for designing the priority logic circuitry 10 in FIG. 1 depending on the desired priorities, if any, which are to be given to the ports P-1, P-2 and P-3. However, known approaches to the design of such priority logic circuitry have been relatively complex and/or expensive.